Si4840/44-A10
t SU:STA t HD:STA
t LOW
t HIGH
t r:IN
t f:IN
t SP
t SU:STO
t BUF
SCLK
SDIO
70%
30%
70%
30%
START
t r:IN
t HD:DAT t SU:DAT
t f:IN,
t f:OUT
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
SDIO
A6-A0,
R/W
D7-D0
D7-D0
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
Rev.1.0
7
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